The present invention relates to a semiconductor memory device with chip layout for enabling high-speed operation. More particularly, the present invention relates to the chip layout of a memory cell chip comprising a plurality of address input circuits, each address input circuit accepting a plurality of address inputs and outputting a complementary signal corresponding to each address input, and a plurality of predecoders, each predecoder outputting selects signal corresponding to the combination of the complementary signals for each two or more address input circuits.
Recently, the development of large-capacity and high-speed memory cell chips has progressed rapidly. The access speed of the memory cell chip is required to be maintained or even to be increased when the capacity of the memory cell chip is increased by 2 or 4 times.
In general, increasing the capacity of the memory cell chip by 4 times entails the increase in the area of the chip by 2 and 3 times. Further, the length of each side of the chip also increases by 1.4 to 2 times. The increase in the chip size resulting from the increase in its capacity entails the elongation of wiring. The elongation of wiring results in the increase in wiring capacity and wiring resistance. These things are now the major drawback to the realization of high-speed operation the memory cell chip.
In general, the access speed is dependent on the time period required from the change of address to the output of the data. That is, the time period during which the address changes to cause the actuation of the address input circuit, establishment of the decoder, selection of one of the cells, amplification of the potential of bit line leading to the cell by the sense amplifier and output of the data of the cell from the data output buffer after passing bus line and the data output circuit.
FIG. 1 schematically illustrates the chip layout of a conventional memory cell chip.
The memory cell chip 100 is divided into 4 cell blocks 101, a pair being arranged horizontally and another horizontally arranged pair coming under the other pair. Row decoder groups 102 are placed between the cell block 101 on the left and the cell block 101 on the right. Column decoder groups 103 and sense amplifier groups 104 are placed between the upper cell block 101 and lower cell block 101 respectively. Further, a pulse synthesizing circuit 105 is provided substantially at the center of the memory cell chip 100. Further, address input circuit groups 106, predecoder groups 107, control pin input circuit 108, data input/output circuit groups 109, data output buffer 110 and a plurality of pads 111 are provided respectively in the peripheral area of the memory cell chip 100. The data input/output circuit groups 109 each comprise a data input circuit and a data output circuit. A plurality of the pads 111 are IO (Input/Output) pads and power source pads.
However, in the case of the previously mentioned conventional layout, the address input circuit groups 106 are provided in the peripheral area of the chip 100. Therefore, the distances between some of the address input circuit groups 106 and some of the predecoder groups 107 are relatively large.
FIG. 2 shows an example of wiring of the chip 100. The figure especially shows wiring 112a-1 connecting address input circuit group 106a and the predecoder group 107a and wiring 112b-1 connecting address input circuit group 106b and predecoder group 107b. Further, the figure shows wiring 112a-2 and wiring 112b-2, respectively ranging from each of the address input circuit for the input of the row address and the address input circuit for the input of the column address to the row decoder and column decoder by way of the predecoder.
In the case of the conventional layout, concerning the row address, wiring 112a-1 (LR1) from the address input circuit group 106a to the predecoder group 107a is relatively long. Further, wiring 112a-2 (LR2) connecting the predecoder group 107a and each of the row decoder groups 102a and 102b is too long. On the other hand, concerning the column address, wiring 112b-1 (LC1) from the address input circuit group 106b to the predecoder group 107b is relatively short. In contrast, wiring 112b-2 (LC2) connecting the predecoder group 107b and column decoder groups 103b and 103d is too long. Therefore, the output signal from the address input circuit group 106a and the output signals from the predecoder groups 107a and 107b are largely affected by the wiring capacity and wiring resistance. This has been a major factor causing a longer time required for the establishment of the decoder and the resultant slow access speed.
Further, similar problem has been encountered as to the pulse signal generated according to the change of address. FIG. 3 shows an example of another wiring for the chip. The figure shows wirings 113a and 113b respectively connecting between the address input circuit group 106a and pulse synthesizing circuit 105 and between the address input circuit group 106b and the pulse synthesizing circuit 105.
The pulse signals generated in the address input circuit groups 106a and 106b respectively are supplied to the pulse synthesizing circuit 105 respectively through wirings 113a and 113b respectively to be used for the formation of pulse synthesizing signal in the pulse synthesizing circuit 105.
The address input circuit groups 106a and 106b are provided in the peripheral area of the chip 100, while the pulse synthesizing circuit 105 is provided substantially at the center of the chip 100. In consequence, the distance from each of the address input circuit groups 106a and 106b to the pulse synthesizing circuit 105 is too large. In this case, the length of wiring 113a (length: LQ1+LQ3) between the address input circuit group 106a and the pulse synthesizing circuit 105 and the length of wiring 113b (length: LQ2+LQ4) between the address input circuit group 106b and the pulse synthesizing circuit 105 are larger than a half of the length of the longer side of the chip 100. In consequence, the pulse signal is affected largely by the wiring capacity and wiring resistance. This has been one of the major hindrances to the quick output of the pulse synthesizing signal.
Further, in the case of the conventional layout (FIG. 1), the distance from the sense amplifier group 104 to the data output buffer 110 by way of the data input/output circuit group 109 is too large. Especially, the length of bus line 114 connecting the sense amplifier group 104 to the data input/output circuit group 109 is extremely too large.
FIG. 4 shows an example of wiring (bus line) for the chip 100, that is, bus line 114a connecting the sense amplifier group 104a to the data input/output circuit group 109a.
The length of bus line 114a, as a wiring, equals to the total of the length (LT1) passing the sense amplifier group 104a, the length (LT2) passing row decoder group 102a and the length (LT3) between the row decoder group 102a and the data input/output circuit group 109a. Consequently, the wiring capacity and wiring resistance of bus line 114a are increased. This has been one of the factors causing the delay of the activation of bus line 114a and the resultant delay of the access speed.
Further, in the case of the conventional layout, the distance between the power source pad and IO pad is too large. Consequently, the wiring resistance of power source line (not shown) increases. This has been one of the factors largely responsible for the dullness of output waveform and resultant low access speed.
As discussed in the foregoing, in the case of conventional chip layout, wiring tends to become unnecessarily long. This has been a major factor responsible for the increase in the wiring capacity and wiring resistance leading to low access speed.